Design and FPGA implementation of PLL-based quarter-rate clock and data recovery circuit

Maher Assaad and Fawnizu Azmadi bin Hussin (2012) Design and FPGA implementation of PLL-based quarter-rate clock and data recovery circuit. [Citation Index Journal]

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Item Type:	Citation Index Journal
Depositing User:	Unnamed user with username haminas3
Date Deposited:	02 Apr 2013 05:24
Last Modified:	07 Apr 2013 03:38
URI:	http://scholars.utp.edu.my/id/eprint/9303

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