Pipelined architecture for low density parity check encoder

Anggraeni, Silvia and Hussin, Fawnizu Azmadi and Jeoti , Varun (2012) Pipelined architecture for low density parity check encoder. In: International Conference on Intelligent and Advanced Systems (ICIAS 2010), 12-14 June, 2012, Kuala Lumpur, Malaysia.

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Official URL: http://dx.doi.org/10.1109/ICIAS.2012.6306129


This paper proposes a pipelined architecture for low density parity check encoder by pipelining information bits and sub-matrices of parity check matrix (H) using two bit-wise operations. The two bit-wise operations are multiplication and exclusive-OR. The investigation is done by exploring two methods of pipelining using the two bit-wise operations in the proposed architecture. The first method of pipelining uses combination of shift register and memory for the sub-matrices of H while the second method of pipelining uses shift register for the information bits and the sub-matrices of H. It is shown that the second method of pipelining increases the throughput but has the largest units of shift registers and flip-flops in the design.

Item Type: Conference or Workshop Item (Paper)
Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
T Technology > TK Electrical engineering. Electronics Nuclear engineering
Departments / MOR / COE: Centre of Excellence > Center for Intelligent Signal and Imaging Research
Departments > Electrical & Electronic Engineering
Research Institutes > Institute for Health Analytics
Depositing User: Dr Fawnizu Azmadi Hussin
Date Deposited: 16 Jan 2013 02:07
Last Modified: 19 Jan 2017 08:21
URI: http://scholars.utp.edu.my/id/eprint/8826

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