The Study of Q-Factor in High Frequency Diode-Clamped Resonant Gate Driver Circuit

The analysis of Q-factor in high frequency resonant
gate driver circuit is presented in this work. It is based on the
variation of resonant inductor values in the diode-clamped
resonant gate driver circuit. At high switching frequency, a
lower value of inductance is preferred. However this will result
in lower Q and high gate resistance power loss. On the other
hand, at higher inductance, gate resistance power loss reduces
but this increases dissipation on the switch. Due to the fact
that Q-factor depends on circuit topology and power switches,
it has become an indicator towards gate driver’s performance.
It is found that Q is optimized at 0.83 for 18 nH, having
satisfied the design inequality equation with lower switching
loss and less oscillation at the switch’s gate voltage. The
simulation work has been carried out using the PSpice
simulation software for 1 MHz switching frequency. Details of
simulation analysis are discussed in the paper.