Highly noise-tolerant design of digital logic gates using Markov Random Field modelling

Anwer, Janhanzeb and Khalid, Usman and Hamid, Nor Hisham and Asirvadam , Vijanth Sagayan and Singh, Narenderjit (2010) Highly noise-tolerant design of digital logic gates using Markov Random Field modelling. In: International Conference on Electronic Computer Technology (ICECT), 2010, 7-10 May 2010, Kuala Lumpur.

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Current trend of downscaling CMOS transistor dimensions is increasing the liability of digital circuits to be easily affected by noise. The resulting unexpected behaviour of our digital devices is due to the low supply voltage of these downscaled circuit elements. Though the low supply voltage decreases the power dissipation of a circuit to a great extent, it decreases the signal to noise ratio as well. The need to transform the conventional logic gates into modified ones having the same functionality but are highly noise-tolerant is catered by the technique Markov Random Field (MRF) modelling proposed in [1]. This paper contributes towards explaining MRF design in a simplified form, proves the error tolerant capability of MRF circuits by simulations performed in Cadence (simulation software) and finally proposes an improvement in the design of [1].

Item Type: Conference or Workshop Item (Paper)
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Q Science > QC Physics
Departments / MOR / COE: Departments > Electrical & Electronic Engineering
Depositing User: Dr Vijanth Sagayan Asirvadam
Date Deposited: 04 Jan 2011 04:28
Last Modified: 01 Apr 2014 06:04
URI: http://scholars.utp.edu.my/id/eprint/3813

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