NBTI-induced 8-Bit DAC circuit mismatch in System-On-Chip (SoC)

Abdul Latif, Mohd Azman and Zain Ali, Noohul Basheer and Hussin, Fawnizu Azmadi (2011) NBTI-induced 8-Bit DAC circuit mismatch in System-On-Chip (SoC). In: 3rd Asia Symposium on Quality Electronic Design (ASQED 2011), 19 - 20 July 2011, Kuala Lumpur, Malaysia.

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This paper focuses on Negative Bias Temperature Instability (NBTI) awareness to the circuit designer for reliable design of the System-On-a-Chip (SoC) analog circuit. The reliability performance of all matched pair such as current source and differential pair circuits, such as Bandgap Reference, is at the mercy of aging differential. Aging simulation (AgingSim) is mandatory to obtain realistic risk evaluation for circuit design reliability qualification. It is applicable to all circuit aging problems covering both analog and digital. Failure rate varies as a function of voltage and temperature. It is shown that PMOS is the reliability-critical device and NBTI is the most critical failure mechanism for analog circuit performance in sub-micrometer CMOS technology. This paper provides a complete reliability simulation analysis of an 8 bit Cathode-Ray-Tube (CRT) Digital-Analog-Converter (DAC) under 90nm process technology and analyze the effect of NBTI using aging simulation tool. A Burn-In experiment was performed to review the reliability sensitivity of the DAC design.

Item Type: Conference or Workshop Item (Paper)
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Departments / MOR / COE: Departments > Electrical & Electronic Engineering
Depositing User: Dr Fawnizu Azmadi Hussin
Date Deposited: 05 Sep 2011 00:38
Last Modified: 19 Jan 2017 08:22
URI: http://scholars.utp.edu.my/id/eprint/6344

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