Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses

Hussin, Fawnizu Azmadi and Yoneda, Tomokazu and Orailoglu, Alex and Fujiwara, Hideo (2007) Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. In: 12th Asia and South Pacific Design Automation Conference (ASP-DAC'07), Jan. 23-26 2007 , Yokohama, Japan.

[thumbnail of fawnizu_aspdac2008.pdf] PDF
fawnizu_aspdac2008.pdf - Published Version
Restricted to Registered users only

Download (224kB) | Request a copy


An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed methodology handles both flat bus single processor SOC and hierarchical bus multiprocessor SOC. It is based on a resource graph manipulation and a packet-based packet set scheduling methodology. The resource graph is decomposed into a set of test configuration graphs, which are then used to determine the optimum test configurations and test delivery schedule under a given power constraint. In order to validate the effectiveness of the proposed methodology, a number of experiments are run on several modified benchmark circuits. The results clearly underscore the advantages of the proposed methodology.

Item Type: Conference or Workshop Item (Paper)
Subjects: T Technology > TK Electrical engineering. Electronics Nuclear engineering
Departments / MOR / COE: Departments > Electrical & Electronic Engineering
Depositing User: Dr Fawnizu Azmadi Hussin
Date Deposited: 23 Dec 2010 08:43
Last Modified: 19 Jan 2017 08:26

Actions (login required)

View Item
View Item