High throughput architecture for low density parity check (LDPC) encoder

Anggraeni, S. and Hussin, F.A. and Jeoti, V. (2013) High throughput architecture for low density parity check (LDPC) encoder. In: UNSPECIFIED.

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Abstract

This paper proposes a bit-wise matrix-vector multiplication in the optimization of a proposed low density parity check (LDPC) encoder. Investigation of this proposed architecture is done by implementing five code lengths using one IEEE 802.16e standard code rate. It is shown that the proposed architecture outperforms other works in terms of information throughput ranging from 0.235 to 8.83 times higher. In term of ratio of throughput per area, the proposed method exceeds other works in the range of 1.19 to 6.54 times higher. © 2013 IEEE.

Item Type: Conference or Workshop Item (UNSPECIFIED)
Impact Factor: cited By 1
Uncontrolled Keywords: Code length; High throughput; Ieee 802.16e standards; Low density parity check; Matrix vector multiplication; Proposed architectures
Depositing User: Ms Sharifah Fahimah Saiyed Yeop
Date Deposited: 30 Mar 2022 01:04
Last Modified: 30 Mar 2022 01:04
URI: http://scholars.utp.edu.my/id/eprint/32691

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